At a time when most smartphone chipsets were manufactured using 7nm technology, Unisoc recently released the world's first 6nm chipset, which was manufactured by TSMC using extreme UV lithography (EUVL). However, other companies are not far behind.
Samsung, the world's second largest chipset manufacturer after TSMC, has already started mass production of EUV (Extreme Ultraviolet) chipsets using 6 nm and 7 nm technology. Now the company has announced that it plans to begin mass production of 5nm chipsets.
The company also added that it will continue to invest in advanced processes, as well as in the 3 nm GAN process. The Samsung V1 factory located in Hwasong, South Korea, will be building production. This is a specialized enterprise using the latest technology, capable of producing chipsets up to 3 nm in size.
There are reports claiming that Google has partnered with Samsung for its own Exynos chipset, which is scheduled to be released this year. The 5nm chipset is expected to have an eight-core processor, consisting of two Cortex-A78 cores, two Cortex-A76 cores and four Cortex-A55 cores.
The undeclared Mali MP20 GPU based on Borr microarchitecture will take care of the graphics. It is also said that it includes Google's own Visual Core provider and NPU instead of Samsung.
A couple of months ago it was reported that the Samsung Electronics semiconductor division won a contract for the manufacture of new Qualcomm 5G chips. This is a serious incentive for a company that seeks to compete with TSMC.
In order to gain leadership among its competitors, Samsung had to start mass production of a 3-nm chipset from 2021, but it seems that the company is now forced to postpone the production launch of this new process until 2022, mainly due to the outbreak of COVID-19.
It is reported that the coronavirus prevented Samsung from completing the planned installation of equipment for new production lines. Samsung's 3nm process is based on Gate All Around (GAAFET) technology, not FinFET. It is estimated that it reduces the total silicon size by 35 percent when using about 50 percent less energy.
It also provides the same energy consumption and 33% increase in performance compared to the 5nm FinFET process. The GAAFET design differs from the FinFET design in that it is built around a gate with four sides of the channel, which provides reduced power leakage and improved channel control.
